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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1853 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 1999 stereo, 24-bit, 192 khz, multibit dac features 5 v stereo audio dac system accepts 16-/18-/20-/24-bit data supports 24 bits and 192 khz sample rate accepts a wide range of sample rates including: 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz and 192 khz mul tibit sigma-delta modulator with ?erfect differential linearity restoration?for reduced idle tones and noise floor data directed scrambling dac?east sensitive to jitter differential output for optimum performance 120 db signal to noise (not muted) at 48 khz (a-weighted mono) 117 db signal to noise (not muted) at 48 khz (a-weighted stereo) 119 db dynamic range (not muted) at 48 khz sample rate (a-weighted mono) 116 db dynamic range (not muted) at 48 khz sample rate (a-weighted stereo) ? 07 db thd+n (mono application circuit, see figure 30) 104 db thd+n (stereo) 115 db stopband attenuation (96 khz) on-chip clickless volume control hardware and software controllable clickless mute se rial (spi) control for: serial mode, number of bits, interpolation factor, volume, mu te, de- emphasis, r eset digital de-emphasis processing for 32, 44.1 and 48 khz sample rates clock auto-divide circuit supports five master-clock frequencies flexible serial data port with right-justified, left- justified, i 2 s-compatible and dsp serial port modes 28-lead ssop plastic package product overview the ad1853 is a complete high performance single-chip stereo digital audio playback system. it is comprised of a high per- formance digital interpolation filter, a multibit sigma-delta modulator, and a continuous-time current-out analog dac section. other features include an on-chip clickless stereo at- tenuator and mute capability, programmed through an spi- compatible serial control port. the ad1853 is fully compatible with all known dvd formats and supports 48 khz, 96 khz and 192 khz sample rates with up to 24 bits word lengths. it also p rovides the ?edbook?standard 50 s/15 s digital de-emphasis f ilters at sample rates of 32 khz, 44.1 khz and 48 khz. the ad1853 has a very flexible serial data input port that allows for glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers and sample rate converters. the ad1853 can be configured in left-justified, i 2 s, right-justified, or dsp serial port compatible modes. the ad1853 accepts serial audio data in msb first, twos complement format. the ad1853 operates from a single +5 v power supply. it is f abricated on a single monolithic integrated circuit and is housed in a 28-lead ssop package for operation over the temperature range 0 c to +70 c. functional block diagram serial data interface 8 f s interpolator serial control interface auto-clock divide circuit volume mute control data input 3 2 digital supply clock in analog outputs 2 2 zero flag analog supply de-emphasis mute reset 2 serial mode digital data input ad1853 multibit sigma- delta modulator atten/ mute idac multibit sigma- delta modulator 8 f s interpolator atten/ mute voltage reference idac int2 int4 applications hi end: dvd, cd, home theater systems, automotive audio systems, sampling musical keyboards, digital mixing consoles, digital audio effects processors
rev. a e2e ad1853especifications test conditions unless otherwise noted supply voltages (av dd , dv dd )+ 5.0 v ambient temperature +25 c input clock 24.576 mhz (512 f s mode) input signal 996.094 khz e0.5 db full scale input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 20 bits input voltage hi 3.5 v input voltage lo 0.8 v analog performance (see figures) min typ max units resolution 24 bits signal-to-noise ratio (20 hz to 20 khz) no filter (stereo) 114 db no filter (mono?see figure 30) 117 db with a-weighted filter (stereo) 117 db with a-weighted filter (mono?see figure 30) 120 db dynamic range (20 hz to 20 khz, e60 db input) no filter (stereo) 107.5 113 db no filter (mono?see figure 30) 116 db with a-weighted filter (stereo) 110 116 db with a-weighted filter (mono?see figure 30) 119 db total harmonic distortion + noise (stereo) e94 e104 db 0.00063 % total harmonic distortion + noise (mono?see figure 30) e107 db 0.00045 % analog outputs differential output range ( full scale w/1 ma into i ref ) 3.0 ma p-p output capacitance at each output pin 30 pf out-of-band energy (0.5 f s to 75 khz) e90 db cmout 2.75 v dc accuracy gain error 3.0 % interchannel gain mismatch e0.15 0.01 +0.15 db gain drift 25 ppm/ c interchannel crosstalk (eiaj method) e125 db interchannel phase deviation 0.1 degrees mute attenuation e100 db de-emphasis gain error 0.1 db notes single-ended current output range: 1 ma 0.75 ma. performance of right and left channels are identical (exclusive of the interchannel gain mismatch and interchannel phase deviat ion specifications). specifications subject to change without notice. digital i/o (+25 ceav dd , dv dd = +5.0 v 10%) min typ max units input voltage hi (v ih ) 2.4 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 3.5 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a input capacitance 20 pf output voltage hi (v oh )dv dd e0.5 dv dd e0.4 v output voltage lo (v ol ) 0.2 0.5 v specifications subject to change without notice.
rev. a e3e ad1853 power min typ max units supplies voltage, analog and digital 4.5 5 5.5 v analog current 12 15 ma digital current 28 33 ma dissipation operation?both supplies 200 mw operation?analog supply 60 mw operation?digital supply 140 mw power supply rejection ratio 1 khz 300 mv p-p signal at analog supply pins e77 db 20 khz 300 mv p-p signal at analog supply pins e72 db specifications subject to change without notice. temperature range min typ max units specifications guaranteed 25 c functionality guaranteed 0 70 c storage e55 125 c specifications subject to change without notice. digital filter characteristics sample rate (khz) passband (khz) stopband (khz) stopband attenuation (db) passband ripple (db) 44.1 dce20 24.1e328.7 110 0.0002 48 dce21.8 26.23e358.28 110 0.0002 96 dce39.95 56.9e327.65 115 0.0005 192 dce87.2 117e327.65 95 +0/e0.04 (dce21.8 khz) +0/e0.5 (dce65.4 khz) +0/e1.5 (dce87.2 khz) specifications subject to change without notice. group delay chip mode group delay calculation f s group delay units int8x mode 5553/(128 f s ) 48 khz 903.8 s int4x mode 5601/(64 f s ) 96 khz 911.6 s int2x mode 5659/(32 f s ) 192 khz 921 s specifications subject to change without notice. digital timing (guaranteed over 0 c to +70 c, av dd = dv dd = +5.0 v 10%) min units t dmp mclk period (with f mclk = 256 f lrclk )* 54 ns t dml mclk lo pulsewidth (all modes) 0.4 t dmp ns t dmh mclk hi pulsewidth (all modes) 0.4 t dmp ns t dbh bclk hi pulsewidth 20 ns t dbl bclk lo pulsewidth 20 ns t dbp bclk period 140 ns t dls lrclk setup 20 ns t dlh lrclk hold (dsp serial port mode only) 5 ns t dds sdata setup 5 ns t ddh sdata hold 10 ns t pdrp pd/rst lo pulsewidth 5 ns *higher mclk frequencies are allowable when using the on-chip master clock auto-divide feature. specifications subject to change without notice.
rev. a ad1853 e4e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1853 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* min max units dv dd to dgnd e0.3 6 v av dd to agnd e0.3 6 v digital inputs dgnd e 0.3 dv dd + 0.3 v analog outputs agnd e 0.3 av dd + 0.3 v agnd to dgnd e0.3 0.3 v reference voltage (av dd + 0.3)/2 soldering +300 c 10 sec *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package characteristics min typ max units ja (thermal resistance [junction-to-ambient]) 109 c/w jc (thermal resistance [junction-to-case]) 39 c/w ordering guide model temperature package description package options ad1853jrs 0 c to +70 c 28-lead shrink small outline rs-28 ad1853jrsrl 0 c to +70 c 28-lead shrink small outline rs-28 on 13" reels pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad1853 filtr outle outl+ agnd iref deemp zeror dgnd mclk clatch cclk int2 int4 cdata fcr outre outr+ avdd filtb idpm1 idpm0 dvdd sdata bclk l/ r clk zerol mute rst
rev. a ad1853 e5e pin function descriptions pin input/output pin name description 1i dgnd digital ground. 2i mclk master clock input. connect to an external clock source. see table ii for allowable frequencies. 3i clatch latch input for control data. this input is rising-edge sensitive. 4i cclk control clock input for control data. control input data must be valid on the rising edge of cclk. cclk may be continuous or gated. 5i cdata serial control input, msb first, containing 16 bits of unsigned data. used for specifying control information and channel-specific attenuation. 6i i nt4 assert hi to select interpolation ratio of 4 , for use with double-speed inputs (88 khz or 96 khz). assert lo to select 8 interpolation ratio. 7i i nt2 assert hi to select interpolation ratio of 2 , for quad-speed inputs (176 khz or 192 khz). assert lo to select 8 interpolation ratio. 8o zeror right channel zero flag output. this pin goes hi when right channel has no signal input for more than 1024 lr clock cycles. 9i deemp de-emphasis. digital de-emphasis is enabled when this input signal is hi. this is used to impose a 50 s/15 s response characteristic on the output audio spectrum at an assumed 44.1 khz sample rate. curves for 32 khz and 48 khz sample rates may be selected via spi control register. 10 i iref connection point for external bias resistor. voltage held at v ref . 11 i agnd analog ground. 12 o outl+ left channel positive line level analog output. 13 o outle left channel negative line level analog output. 14 o filtr voltage reference filter capacitor connection. bypass and decouple the voltage refer- ence with parallel 10 f and 0.1 f capacitors to the agnd (pin 11). 15 i fcr filter cap return pin for cap connected to filtb (pin 19). 16 o outre right channel negative line level analog output. 17 o outr+ right channel positive line level analog output. 18 i avdd analog power supply. connect to analog +5 v supply. 19 o filtb filter capacitor connection, connect 10 f capacitor to fcr (pin 15). 20 i idpm1 input serial data port mode control one. with idpm0, defines one of four serial modes. 21 i idpm0 input serial data port mode control zero. with idpm1, defines one of four serial modes. 22 o zerol left channel zero flag output. this pin goes hi when left channel has no signal input for more than 1024 lr clock cycles. 23 i mute mute. assert hi to mute both stereo analog outputs. deassert lo for normal operation. 24 i rst reset theiseiesetsttehethisiishetheis esettheisigegethissigtheseittegisteseesettthe eteseteti r et right itittsttis itititt st seiitsisttiigthesittseet t igitesettigits
rev. a ad1853 e6e sdata input lsb msbe2 msbe1 lsb+2 lsb+1 m sbe2 m sbe1 msb l sb+2 lsb+1 lsb bclk input l/ r clk input left channel right channel msb lsb figure 1. right-justified mode left channel right channel msbe2 msbe1 lsb+2 lsb+1 lsb msbe2 msbe1 msb lsb+2 lsb+1 lsb msb l/ r clk input bclk input sdata input msb figure 2. i 2 s-justified mode msbe2 msbe1 lsb+2 lsb+1 lsb msbe2 msbe1 msb lsb+2 lsb+1 lsb msbe1 msb l/ r clk input bclk input sdata input left channel right channel msb figure 3. left-justified mode sdata input msbe1 lsb+2 lsb+1 lsb msbe1 lsb+2 lsb+1 lsb msb msbe1 msb l/ r clk input left channel right channel bclk input msb figure 4. left-justified dsp mode l/ r clk input left channel right channel bclk input sdata input lsb msbe1 msbe2 lsb+2 lsb+1 lsb msb msbe1 msbe2 lsb+2 lsb+1 lsb msb msbe1 msb figure 5. 32 f s packed mode
rev. a ad1853 e7e operating features serial data input port the ad1853?s flexible serial data input port accepts data in twos-complement, msb-first format. the left channel data field always precedes the right channel data field. the serial mode is set by using either the external mode pins (idpm0 pin 21 and idpm1 pin 20) or the mode select bits (bits 4 and 5) in the spi control register. to control the serial mode using the external mode pins, the spi mode select bits should be set to zero (de fault at power-up). to control the serial mode using the spi mode select bits, the external mode control pins should be grounded. in all modes except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated inter- nally). in the right-justified mode, control register bits 8 and 9 are used to set the word length to 16, 20, or 24 bits. the default on power-up is 24-bit mode. when the spi control port is not being used, the spi pins (3, 4 and 5) should be tied lo. serial data input mode the ad1853 uses two multiplexed input pins to control the mode configuration of the input data port mode. table i. serial data input modes idpm1 idpm0 (pin 20) (pin 21) serial data input format 00 right justified (24 bits) default 01i 2 s-compatible 10 left justified 11 dsp figure 1 shows the right-justified mode. lrclk is hi for the left channel, lo for the right channel. data is valid on the rising edge of bclk. in normal operation, there are 64-bit clocks per frame (or 32 per half-frame). when the spi word length control bits (bits 8 and 9 in the control register) are set to 24 bits (0:0), the serial port will begin to accept data starting at the 8th bit clock pulse after the l/ r tsitihetheegthtits esettitetisetesttigtthethit sitiitetisetesttigtthe thitsititheseeseieeetthe eitseetheeethetts essiesigtheeesesieeetie tiigseeige igeshsthe se r istheeth etheighthetisitheisig egethesisetstiiet r tsi titithsigeeiethe see seteteitst igeshstheetstiiee r isthe ethetheighthetisithe isigegethesisetstiiet r tsitiithsetheetstiiee etegthtits igeshsthesseite r stse testeiteieethestheet heisi r stsegitest eiteieethestheightheis itisitheigegethessei teeseithegthtits t s r st t st st r tst s st s st t t t t s s s t t s s t t s t s t t s ts tt ts tt ts tt ige seitttiig
rev. a ad1853 e8e in this mode, it is the responsibility of the dsp to ensure that the left data is transmitted with the first lrclk pulse, and that synchronism is maintained from that point forward. note that the ad1853 is capable of a 32 f s bclk frequency packed mode where the msb is left-justified to an l/ r tsitithesisightstiietthesite r tsiti r istheethethe ighthetisitheisigegee eesehetheisgeiight stiieetstiieeeeisshisige stetiieete thehsiitthttetetstheetishi eteestetheiigseitite setstheetiietittheitet ttheeeeieseheesh e seitt theseittisstiessei eiheteeisiststseitt theiteseittgiestheseesstseet itestesetsteehsisheseiit tetitethhestethestis ieiteeithseitt seiit tthtthetise ititeshitegistetheisigege theseitshhgetheigege e stetheisigegetheisigege tis seitetththeetthe seiteetethisisigegesheige iththeigegethestseitheite thetiseteetstis theseittisitsistissigeits esetseetegistesteet eighttheeiigitsitseset thettheseeteegisteeegisteis seetethetheeitsesettitheigit itsigthethihisiteetes sigeeeeis isettheetet seesthetegiste sesitstttheeitssh seitteitheessseetesteseee theseeitsthetegisteetse t itetieitightstiieseie teeehsisitetheitetiththeseeset etsisteeitisithteiigthe setheseittthsesesthttsethe seittitisstissiettethett sigthetiisig tethttheseitttiigisshstthe seitttiighgesetthettetee ietetheetegethertet itesesshiige te it tesiget hie esteeeies serte rte t e s s s s s s t e s s s s s s t e s s s s s s t t t s t t t t t ige seitttiig
rev. a ad1853 e9e table iii. digital timing min units t cch cclk hi pulsewidth 40 ns t ccl cclk low pulsewidth 40 ns t csu cdata setup time 10 ns t chd cdata hold time 10 ns t cll clatch low pulsewidth 10 ns t clh clatch hi pulsewidth 10 ns spi register definitions the spi port allows flexible control of many chip parameters. it is organized around three registers; a left-channel volume register, a right-channel volume register and a control register. each write operation to the ad1853 spi control port requires 16 bits of serial data in msb-first format. the bottom two bits are used to select one of three registers, and the top 14 bits are then written to that register. this allows a write to one of the three registers in a single 16-bit transaction. the spi cclk signal is used to clock in the data. the incom- ing data should change on the falling edge of this signal. at the end of the 16 cclk periods, the clatch signal should rise to latch the data internally into the ad1853. register addresses the lowest two bits of the 16-bit input word are decoded as follows to set the register into which the upper 14 bits will be written. bit 1 bit 0 register 00v olume left 10v olume right 01c ontrol register volume left and volume right registers a write operation to the left or right volume registers will acti- vate the auto-ramp clickless volume control feature of the ad1853. this feature works as follows. the upper 10 bits of the volume control word will be incremented or decremented by 1 at a rate equal to the input sample rate. the bottom 4 bits are not fed into the auto-ramp circuit and thus take effect immedi- ately. this arrangement gives a worst-case ramp time of about 1024/f s for step changes of more than 60 db, which has been determined by listening tests to be optimal in terms of pre- venting the perception of a click sound on large volume changes. see figure 8 for a graphical description of how the volume changes as a function of time. the 14-bit volume control word is used to multiply the signal, and therefore the control characteristic is linear, not db. a con- stant db/step characteristic can be obtained by using a lookup table in the microprocessor that is writing to the spi port. 20ms time e60 e60 0 0 level e db volume request register actual volume register figure 8. smooth volume control
rev. a ad1853 e10e control register the following table shows the functions of the control register. the control register is addressed by having a 01 in the bottom 2 bits of the 16-bit spi word. the top 14 bits are then used for the control register. bit 11 bit 10 bit 9:8 bit 7 bit 6 bit 5:4 bit 3:2 int2 m ode int4 mode number of soft reset. soft mute or?d serial mode or?d de-emphasis filter or?d with pin. or?d with pin. bits in right- default = 0 with pin. with mode pins. select. default = 0 default = 0 justified serial default = 0 idpmi:idpm0 0:0 no filter mode. 0:0 right-justified 0:1 44.1 khz filter 0:0 = 24 0:1 i 2 s 1:0 32 khz filter 0:1 = 20 1:0 left-justified 1:1 48 khz filter 1:0 = 16 1:1 dsp mode default = 0.0 default = 0:0 default = 0:0 mute the ad1853 offers two methods of muting the analog output. by asserting the mute (pin 23) signal hi, both the left and right channel are muted. as an alternative, the user can assert t he mute bit in the serial control register (bit 6) hi. the ad1853 has been designed to minimize pops and clicks when muting and unmuting the device by automatically ramping the gain up or down. when the device is unmuted, the volume returns to the value set in the volume register. analog attenuation the ad1853 also offers the choice of using iref (pin 10) to attenuate by up to 50 db in the analog domain. this feature can be used as an analog volume control. it is also a convenient place to add a compressor/limiter gain control signal. output drive, buffering and loading the ad1853 analog output stage is able to drive a 1 k (in series with 2 nf) load. the analog outputs are usually ac coupled with a 10 f capacitor. de-emphasis the ad1853 has a built-in de-emphasis filter that can be used to decode cds that have been encoded with the standard redbook 50 s/15 s emphasis response curve. three curves are available; one each for 32 khz, 44.1 khz and 48 khz sam- pling rates. the external deemp pin (pin 9) turns on the 44.1 khz de-emphasis filter. the other filters may be selected by writing to control bits 2 and 3 in the control register. if the spi port is used to control the de-emphasis filter, the external deemp pin should be tied lo. control signals the idpm0 and idpm1 control inputs are normally con- nected hi or lo to establish the operating state of the ad1853. they can be changed dynamically (and asynchronously to lrclk and the master clock), but it is possible that a click or pop sound may result during the transition from one serial mode to another. if possible, the ad1853 should be placed in mute before such a change is made. figures 9e14 show the calculated frequency response of the digital interpolation filters. figures 15e27 show the performance of the ad1853 as measured by an audio precision system 2 cascade. for the wideband plots, the noise floor shown in the plots is higher than the actual noise floor of the ad1853. this is caused by the higher noise floor of the high bandwidth adc used in the audio precision measurement system. the two-tone test shown in figure 18 is per the smpte standard for measur- ing intermodulation distortion. frequency e khz 0.001 0 db 21012141620 0.0008 0.0006 0.0004 0.0002 0 e0.0002 e0.0004 e0.0006 e0.0008 e0.001 468 18 figure 9. passband response 8 mode, 48 khz sample rate frequency e khz 0 attenuation e db e60 e100 e160 e20 e40 e80 e120 e140 0 150 200 50 100 250 300 350 figure 10. complete response, 8 mode, 48 khz sample rate
rev. a ad1853 e11e t ypical performance characteristicse frequency e khz 0.5 e10 db 510152 025303540 0.4 0.3 0.2 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 figure 11. 44 khz passband response 4 mode, 96 khz sample rate frequency e khz 2.0 1.5 1.0 0 db 0 e0.5 e1.0 e2.0 10 20 30 40 50 60 70 80 e1.5 0.5 figure 12. 88 khz passband response 2 mode, 192 khz sample rate frequency e hz 10 dbr e120 100 1k 10k e110 e100 e90 e80 e70 e60 e50 figure 13. thd vs. frequency input @ e3 dbfs, sr 48 khz 0 0 db 150 200 e60 e100 50 100 250 e20 e40 e80 e120 e140 300 frequency e khz e160 figure 14. complete response, 4 mode, 96 khz sample rate frequency e khz 0 db e60 e120 e160 e40 e20 e80 e100 e140 0 150 200 50 100 250 figure 15. complete response, 2 mode, 192 khz sample rate dbfs db e80 e90 e100 e110 e70 e60 e50 e40 e30 e20 e10 0 e120 e100 e80 e60 e40 e20 0 figure 16. thd + n ratio vs. amplitude input 1 khz, sr 48 khz, 24-bit
rev. a ad1853 e12e frequency e hz 10 dbr e12 100 1k 10k e10 e8 e6 e4 e2 0 2 figure 17. normal de-emphasis frequency response input @ e10 dbfs, sr 48 khz frequency e khz dbr e90 e110 e130 e150 e70 e50 e30 e10 0 246810121416182022 figure 18. smpte/din 4:1 imd 60 hz/7 khz @ 0 dbfs dbfs dbr e80 e100 e120 e140 e60 e40 e20 0 e140 e120 e100 e60 e40 e20 0 e80 figure 19. linearity vs. amplitude input 200 hz, sr 48 khz, 24-bit word frequency e khz dbr e130 e140 e150 e120 e110 e100 e90 0246810 12 14 16 18 20 22 e80 e70 e60 e50 e40 e30 e20 e10 0 figure 21. input 0 dbfs @ 1 khz, bw 10 hz to 22 khz, sr 48 khz, thd+n 104 dbfs frequency e khz dbr e130 e140 e150 e120 e110 e100 e90 0 246810121416182022 e80 e70 e60 e50 e160 figure 22. dynamic range for 1 khz @ e60 dbfs, 116 db, triangular dithered input frequency e khz dbr e130 e140 e150 e160 e120 e110 e100 e90 0 246810121416182022 figure 20. noise floor for zero input, sr 48 khz, snr e117 dbfs a-weighted
rev. a ad1853 e13e frequency e hz 10 dbr e100 e90 e60 100 1k 10k e70 e80 figure 23. power supply rejection vs. frequency av dd 5 v dc + 100 mv p-p ac frequency e khz 0 e100 120 20 dbr 40 60 80 100 e10 e40 e70 e80 e90 e20 e30 e50 e60 e110 e120 e130 e140 figure 24. wideband plot, 15 khz input, 8 interpolation, sr 48 khz frequency e khz 0 e100 120 20 dbr 40 60 80 100 e10 e40 e70 e80 e90 e20 e30 e50 e60 e110 e120 e130 e140 figure 25. wideband plot, 37 khz input, 4 interpolation, sr 96 khz frequency e khz 0 e100 30 5 dbr 10 15 20 25 e10 e40 e70 e80 e90 e20 e30 e50 e60 e110 e120 e130 e140 e150 e160 35 40 45 50 55 60 65 70 75 80 figure 26. wideband plot, 25 khz input, 2 interpolation, sr 192 khz frequency e khz 0 e100 30 5 dbr 10 15 20 25 e10 e40 e70 e80 e90 e20 e30 e50 e60 e110 e120 e130 e140 e150 e160 35 40 45 50 55 60 65 70 75 80 figure 27. wideband plot, 75 khz input, 2 interpolation, sr 192 khz
rev. a ad1853 e14e stereo mode output filter hdr3 f n 12 44/48 0 0 96 1 0 192 0 1 no 1 1 c37 47pf c11 100nf dvdd c24 47nf r4 1k dvdd avdd outr+ outre outl+ outle filtb dgnd agnd fcr u5 ad1853jrs c26 10 f c56 100nf signal source j1 r3 750 r1 75 r8 10k r7 10k r9 10k c9 100nf dvdd c8 100nf avdd dvdd ds1 zero left c10 100nf fb3 600z note: = dgnd = agnd int4 int2 sdata l/ r clk bclk mclk idpm0 idpm1 deemp mute clatch cclk cdata zeror zerol rst filtr iref clatch cclk cdata zr zl rst + e r28 2.67k agnd dgnd sample rate mode r5 10k r6 10k dvdd r19 10k clk/i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i /o9 i/o8 i /o7 i /o6 i /o5 i /o4 i /o3 i /o2 i/o1 i/o0 u4 palce22v10-j mclk ext mclk ext sclk ext l/ r clk ext sdata hdr3 r18 10k 3 8 idpm1 dvdd r17 10k 2 9 idpm0 dvdd s2b s2c vref r23 274 q1 2n2222 ds4 dvdd verf preemph 1 2 3 dvdd u3a 74hc00d c5 100nf dvdd c6 100nf sdata fsync sck mck m0 m1 m2 m3 c u cbl verf erf c0 /e0 ca/e1 cb/e2 cc/f0 cd/f1 ce/f2 sel c s i2/fck dgnd agnd va+ vd+ fb2 600z r24 100 r12 10k c35 47pf r25 100 r13 10k c36 47pf r26 100 r14 10k c34 47pf r27 100 r15 10k ext sdata ext l/ r clk ext sclk ext mclk dvdd r11 10k 1 10 dvdd s2a spdif/ ex t spdif/ext i/f select rout+ route lout+ loute v ref +2.7v hdr2 ext i/f in f s 64f s 256f s u2 cs8414-cs 12 13 11 u3d 74hc00d set ib = 1ma ds2 zero right r21 274 9 10 8 u3c 74hc00d ds3 deemph r22 274 4 5 6 u3b 74hc00d dvdd r20 274 dvdd c12 100nf zr zl filt c1 10nf s1 c2 10nf rxp rxn 1 0 spnif in dgnd shld dgnd u1 torx173 out dvdd toslink in c4 100nf r2 3.40k 500mvp-p fb1 600z dvdd r10 10k mute r16 10k 4 7 deemph dvdd s2d on off deemph 5 6 mute s2e off on cdata cclk clatch mclk dvdd hdr1 ext c i/f 1 2 3 4 5 10 u2 data source i 2 s serial data mode deemph off mute off s2a s2b s2c s2d s2e #98107-02-3 rev. 1.1 1 1 figure 28. digital receiver, mux and ad1853 dac
rev. a ad1853 e15e u8b op275 c38 220pf np0 r29 2.94k r41 604 r34 2.74k c43 680pf np0 r33 2.74k c42 680pf np0 r30 2.94k r35 2.74k r36 2.74k c39 220pf np0 c50 2.2nf np0 right out j2 1 gaussian filter response e3db corner frequency: 75khz output buffers and lp filters 0 r43 49.9k c46 330pf, np0 c52* np c21 100nf eav ss c23 100nf +av cc op275 u6a r48 4.12k u6b op275 c53* np c47 330pf, np0 r49 4.12k c57 220pf np0 + e c7 100nf u8a op275 c40 220pf np0 r31 2.94k r42 604 r38 2.74k c45 680pf np0 r37 2.74k c44 680pf np0 r32 2.94k r39 2.74k r40 2.74k c41 220pf np0 c51 2.2nf np0 left out j3 1 0 r44 49.9k c48 330pf, np0 c54* np c20 100nf eav ee c22 100nf +av cc op275 u7a r50 4.12k u7b op275 c55* np c49 330pf, np0 r51 4.12k c58 220pf np0 c19 100nf eav ss c18 100nf +av cc r52 402 r53 402 c25 10 f rout+ lout+ loute v ref +2.7v avdd agnd +15v dc ds5 power fb4 600z in in err sd out out nr gnd +av cc j6 u11 adp3303-5.0 c3 10nf c16 100nf + e c31 10 f + e c30 10 f c15 100nf + e c32 10 f +5v reg r47 332 eav ss cr2 1smb15at3 0v agnd j7 + e c33 10 f e15v dc j8 voltage regulators and supply filtering dvdd +9v dc to +15v dc fb5 600z j4 u9 lm317 + e c29 10 f + e v in r46 715 cr1 1smb15at3 0v dgnd j5 + e c28 10 f v out gnd r45 243 +5v reg dgnd c13 100nf c27 10 f cr3 1n4001 c14 100nf dvdd pfi mr v cc reset reset pfo gnd rst u10 adm707ar s3 reset c17 100nf reset generator note: = dgnd = agnd *not populated route figure 29. dac output lp filter, power and reset
rev. a ad1853 e16e c3503ae8e4/99 printed in u.s.a. u1 ad797 c1 220pf np0 r1 2.94k r7 604 r4 2.74k c4 680pf np0 r3 2.74k c3 680pf np0 r2 2.94k r5 2.74k r6 2.74k c2 220pf np0 c5 2.2nf np0 gaussian filter response e3db corner frequency: 75khz i /v converters and lp filter r8 49.9k c6 68pf, np0 ad797 u2 r9* 2.87k u3 c7 68pf, np0 r10* 2.87k + e c8 100nf r12 100 pin 13 loute pin 12 lout+ v ref +2.78v r11 100 ad797 out 6vrms j1 1 0 pin 16 route pin 17 rout+ notes: 1. r9, r10 must be low noise types. metal film is recommended. 2. right channel digital data must be inverted. c15 10 f tant +av cc eav ss j2 + e c14 100nf 0v agnd j4 + e c17 10 f tant j3 c13 100nf c16 10 f tant c12 100nf c11 100nf c10 100nf c9 100nf +16.5v dc e16.5v dc note: = agnd figure 30. mono application circuit outline dimensions dimensions shown in inches and (mm). 28-lead shrink small outline package (ssop) (rs-28) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8? 0? 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) seating plane 0.0256 (0.65) bsc 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 15 14 1 0.407 (10.34) 0.397 (10.08) pin 1

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